Logical gates subjects list ▲
Boolean algebra laws Boolean algebra calculator Karnaugh 3 & 4 variables tables
Logical gates symbols Karnaugh maps Seven Segment Decoder
Empty Karnaugh maps
Logical gates overview Print logical gates overview ▲
Logical gates are the basic of the computerized world and is based on the digital values of the binary numbers  0  and  1. The implementation of the logical gates are performed by the rules of the Boolean algebra, and based on the combinations of the operations  OR, AND  and  NOT. The specific gate operation is attained by using diodes or transistors that acts like a switch  0  is off  (0 Volt)  and  1  is on  (5 Volt).
Logical OR and AND gates description
Operation Logical symbol Switch operation Electronics
OR OR gate symbole
0
AND AND gate symbole
Logical gates examples 1, 2 and 3 Print logical gates example 3 ▲
F(X, Y,Z) = XY' + Z
Num X    Y    ZXY'Output
10    0    000
20    0    101
30    1    000
40    1    101
51    0    011
61    0    111
71    1    000
81    1    101
Num A    BOutput
10    01
20    11
31    00
41    10
Output
From the output result we can see that the system can be simplified to the equivalent form.
F(A, B) = A XOR B
NumA     BOutput
10     00
20     11
31     01
41     10
Output
This system is the equivalent of the XOR gate.
Seven-segment Decoder ▲
Segment:

A seven-segment display is an electronic device for displaying decimal numbers. widely used for electronic clocks and counters. The display is designed by using logical gates.
Each segment of the number can be calculated by using the Karnaugh method (see above).

Logical gates example 4 Print logical gates example 45 ▲
Example 5
The truth table at points  D, E, F, G, H and K  of the system described above are.

ABCDEFGHK
000000000
000100100
001000000
001100100
010001100
010100100
011001100
011100100
100000000
100100111
101000000
101100111
110011111
110110111
111001111
111100111
Port Value Notes
E A AND B AND NOT C
F B AND NOT D
G D OR F D + F
H A AND G A‧G
K E OR H E + H
Logical gates example 5 Print logical gates example 5 ▲
Example 3
The truth table at points  D, E, F, G, H, I, J, and K  of the system described above are.

ABCDEFGHIJK
00011100110
00111010100
01010110100
01110010100
10001110100
10101010100
11000110100
11100011011
Port Value Notes
D NOT A NOT Buffer
E NOT B NOT Buffer
F NOT C NOT Buffer
G NOT (D AND E AND F) De Morgan's theorem
H NOT (D OR E OR F) NOT (D OR E OR F)
I NOT (A AND B AND C) NOT (D AND E AND F)
J NOT (G XNOR H)
K NOT (D OR E OR F) NOT (D OR E OR F)
Logical gates example 6 Print logical gates example 6 ▲
Example 7
The truth table at points  C, D, E, F and G  of the system described above are.

ABCDEFG
0001000
0101101
1001101
1111000
Port Value
C A AND B
D
NOT A AND B
NOT A AND B
E A XOR B
F NOT (A AND B OR 1)         (D equals 1 see above)
G D AND (A XOR B)
Logical gates example 7 Print logical gates example 7 ▲
Example 7
The truth table at points  D, E, F, G, H and K  of the system described above are.

ABCDEFGHK
000000000
001000111
010110011
011111101
100100010
101100000
110000000
111001011
Port Value Notes
D A XOR B
E NOT A AND B
F B AND C
G NOT A AND C)
H A XOR B XOR C
K NOT A AND B OR B AND C OR NOT A AND C
Logical gates example 8 - 4 bit comparator Print logical gates example 8 ▲
Example 8 1 2 3 4 5 6 7 8
If the 4 bits at the upper left side are the same as the 4 bits at the lower left side, then the output is 1 (green) else the output is 0 (red).
Logical gates 4 bits left shift example 9 Print logical gates example 9 ▲
Example 9 1 2 3 4 5 6 7 8
Left shift is performed by moving all the bits one place to the left and filling  0  in the last place, most left bit is lost or moved to the next higher level.
For example, the byte   10011001   after left shift will be:   00110010
If we remember the most left bit, the left shift operation is equivalent to multiplying the number by  2. For example the byte  00001110  equals  14 decimal, after left shift we get  00011100  which is equal to 28.
Draw logical gate circuit from Boolean expression example 11 Print logical gates example 11 ▲
If we have a logical expression such as NOT (A AND B) we can draw the equivalent
logical gate circuit by the following steps:
1 Divide the expression into 2 expressions separated by the OR (+) operator marked by X and Y.
NOT (A AND B) this is equivalent to the gate: X OR Y
2
The X expression can be divided into AND gate after simplifying:
X = (NOT A AND B) AND NOT A this expression is the gate: NOT (A AND B)
3
Perform the same process on the  Y  expression to get an  AND  of  2  expressions:
X = (NOT A AND B) AND NOT A this expression is the gate: NOT (A AND B)
4
Combine the gates of section 1, 2 and 3 to get the final scheme of the complete gate:
NOT (A AND B)
Half adder example 12 Print full adder example 12 ▲
General Half Adder

The half adder performs the addition of two bits with an XOR gate and return a carry with an AND gate in case that both A and B are equal to 1.

General half adder true table

The difference between Half Adder and Full Adder is the input of a carry to the Full Adder, three inputs (see example 12a). After calculation they both return the sum and a carry.
Full adder example 12a Print full adder example 12 ▲
Example 12
The full adder adds the values of two bits  A  and  B,  if both bits are equal to 1 then it passed through the value of the carry to the next calculation level. For the first loop (rightmost bit) the input carry equals to 0. In order to add two bytes, we can add 8 full adders (see next example).
The truth table for full adder is:

Carry-inABDEFSumCarry-out
00000000
00110010
01010010
01100101
10000010
10111001
11011001
11100111
For example 2 bits A and B
X = (NOT A AND B) AND NOT A
X = (NOT A AND B) AND NOT A
Port Value
D A'·B + A·B'
E C·D = C·(A'·B + A·B') = C·A'·B + C·A·B'
F A·B
Sum Sum output
Carry-out Carry output
Full adder draw with 7408, 7432 and 7486 chips Print full adder draw with 7408, 7432 and 7486 chips ▲
The basic circuit for adding two bits contains the chips IC 7486 - quad XOR gate, IC 7408 - quad AND gate and IC 7432 quad OR gate. We used only half of the gates of the XOR and AND gates and only 1 of the OR gate. All the chips have to be connected to the input voltage at Vcc and to the ground at GND input.
The carry out values can be connected to the carry input of the next pair of bits and so on until we reach the number of bits that should be added, see next example for 4 bits addition, this case uses all the inputs of the three types of chips 7486, 7408 and 7432.
Full adder draw with 7408, 7432 and 7486 chips Print full adder draw with 7408, 7432 and 7486 chips ▲
The basic circuit for adding two bits contains the chips IC 7486 - quad XOR gate, IC 7408 - quad AND gate and IC 7432 quad OR gate. We used only half of the gates of the XOR and AND gates and only 1 of the OR gate. All the chips have to be connected to the input voltage at Vcc and to the ground at GND input.
The carry out values can be connected to the carry input of the next pair of bits and so on until we reach the number of bits that should be added, see next example for 4 bits addition, this case uses all the inputs of the three types of chips 7486, 7408 and 7432.
4 bits adder example 13 Print 4 bits adder example 13 ▲
Example 13
0
0
0
The 4 bits adder adds the values of two 4 bits values and gives the result at right, notice that the result contains additional carry that can be used for the next higher calculations. This process can be easily extended to more bits.


Example - Add the  4  bits binary number  1011 (decimal 11)  to the binary number  0110 (decimal 6)..
Binary 1011 + 0110 = 10001 Notice that in binary addition
        0 + 0 = 0
        0 + 1 = 1
        1 + 1 = 0     and carry 1.
2 bits multiplier example 14 Print 4 bits adder example 14 ▲
0
×
0
=
0
Sum output
Let multiply two bits first bit is:  (1 0) and the second bit is:  (1 1) the result of this multiplication is: Multiplication example
The multiplication is made according to the following rules: Multiplication example Multiplication example

The general process of multiplying two sets of two bits (a1 a0) and (b1 b0) is according to the following steps:

General 2 bits multiplication

In order to better understand the circuit of the set of two, two bits multiplier we draw the circuit with the half adder as a box, now we can see clearly way the calculations take place.

General 2 bits multiplication

1) The result of the first multiplication is the value of c0 = a0b0 (blue line).

2) Now perform the addition of c1 = a1 b0 ⨁ a0 b1. This operation is performed by the half adder no. 1 circuit because it gets two values which are not including a carry from c0. (see example 12). The result sum is the value of c1 (yellow line).

3) Now perform the addition of c2 = a1 b1 ⨁ carry. This operation is performed by the half adder no. 2 circuit notice that one input is the result of the carry from half adder number 1. The sum is the value of c2 (green line).

4) The result of the carry of the second adder is the value of c3 (red line).